8.0 CIRCUITS FOR THE ARITHMETICAL OPERATIONS −, ÷ #

8.1 #

Until now a number x was a sequence of (about 30) binary digits, with no definition of sign or binary point. We must now stipulate conventions for the treatment of these concepts.

The extreme left digit will be reserved for the sign, so that its values 0,1 express the signs +, −, respectively. If the binary point is between the digital positions i and i + 1 (from the left), then the positional value of the sign digit is \(2^{i−1}\) . Hence without the sign convention the number x would lie in the interval \(0 ≤ x < 2^{i}\) , and with the sign convention the subinterval \(0 ≤ x < 2^{i−1}\) is unaffected and corresponds to non-negative numbers, while the interval \(2^{i−1} ≤ x < 2^i\) corresponds to negative numbers. We let the latter x represent a negative xj, so that the remaining digits of x are essentially the complements to the digits of −xj. More precisely:
\(2^{i−1} − (−x') = x − 2^{i−1}\) , that is \(x' = x − 2^i\) , for \(x'\) in the interval \(−2^{i−1} ≤ x' < 0\) .

In other words: The digital sequences which we use represent, without the sign convention, the interval 0 ≤ x < 2i, and with the sign convention the interval \(−2^{i−1} ≤ x < 2^{i−1}\) . The second interval is correlated to the first one by subtracting \(2^{i}\) if necessary—that is their correspondence is modulo \(2^{i}\) .

Since addition and subtraction leave relations modulo \(2^{i}\) unaffected, we can ignore these arrangements in carrying out additions and subtractions. The same is true for the position of the binary point: If this is moved from i to ij, then each number is multiplied by \(2^{i−i}\) , but addition and subtraction leave this relation invariant too. (All these things are, of course, the analogs of the conventional decimal procedures.)

Thus we need not add anything to the addition procedure of 7.3, and it will be correct to set up a subtraction procedure in the same way. The multiplication procedure of 7.7, however, will have to be reconsidered, and the same caution applies to the division procedure to be set up.

8.2 #

We now set up a subtracter network. We can use the adder (cf. 7.3) for this purpose, if one addend—say the first one—is fed in the negative. According to the above this means that this addend x is replaced by \(2^i − x\) . That is each digit of x is replaced by its complement, and a unit of the extreme right digital position is then added to this addend—or just as well as an extra addend.

This last operation can be carried out by stimulating the extra input c of the adder (cf. Figure 3) at that time. This takes automatically care of all carries which may be caused by this extra addition.

The complementation of each digit can be done by a valve which does the opposite of that of Figure 7: When stimulated at s, it passes the complement of the main stimulus from is to os: Figure 10.

Now the subtracter network is shown in Figure 11. The subtrahend and the minuend come in on the input lines s, m, and the difference is emitted with a delay 3t against the inputs on the output line d. The two inputs t’, t’’ receive the necessary timing stimuli: t’ throughout the period of subtraction, t’’ at its first t (corresponding to the extreme right digital position, cf. above).

8.3 #

Next we form a divider network, in the same preliminary sense as the multiplier network of 7.7.

Binary division consists of this: For each digital position in the quotient (going from left to right), the divisor is subtracted from the partial remainder (of the dividend) already formed; but which has been shifted left by one position, preceding this subtraction. If the resulting difference is not negative (that is, if its extreme left digit is 0) then the next quotient digit is 1, and the next partial remainder (the one to be used for the following quotient digit, before the shift left referred to above) is the difference in question. If the difference is negative (that is, if its extreme left digit is 1) then the next quotient digit is 0, and the next partial remainder (in the same sense as above) is the preceding partial remainder, but in its shifted position.

The alternative in division is therefore comparable to the one in multiplication (cf. 7.7), with this notable difference:

In multiplication it was a matter of passing or not passing an addend: the multiplicand. In division the question is which of two minuends to pass: the (shifted) preceding partial remainder, or this quantity minus the divisor. Hence we now need two valves where we needed one in multiplication. Also, we need a discriminator which is somewhat more elaborate than the one of Figure 8: It must not only pass a sequence of stimuli from is to os if there was a stimulus at s at the moment defined by the stimulation of t, but it must alternatively pass that sequence from is to another output osj if there was no stimulus at s at the moment in question. Comparison of Figure 8, with Figure 12 shows, that the latter possesses the desired properties. The delay between is and os or osj is now 3t.

Now the divider network can be put together: Figure 13. The divisor circulates through \(\boxed{dl Ⅰ}\) , while the dividend is originally in \(\boxed{dl Ⅲ}\) , but is replaced, as the division progresses, by the successive partial remainders. The valve \(\boxed{v_{-1}}\) routes the divisor negatively into the adder. The two valves \(\boxed{v_1}\) immediately under it select the partial remainder (cf. below) and send it from their common output line on one hand unchanged into the sum (actually the difference) goes required one position shift left. Thus and on the other hand into the adder, from where ming must be such as to produce the contain the two numbers from among

which the next partial remainder is to be selected. This selection is done by the discriminator which governs the two valves controlling the (second addend) input of the adder (cf. above). The sign digit of the resulting sum controls the discriminator, the timing stimulus at t must coincide with its appearance (extreme left digit of the sum). t’ must be stimulated during the period in which the two addends (actually minuend and subtrahend) are to enter the adder (advanced by 3t). t’’ must receive the extra stimulus required in subtraction (t’’ in Figure 11) coinciding with the extreme right digit of the difference. The quotient is assembled in , for each one of its digits the necessary stimulus is available at the second output of the discriminator (osj in Figure 12). It is passed into \(\boxed{dl Ⅳ}\) through the lowest valve \(\boxed{v_1}\) , timed by a stimulus at t’’'.

8.4 #

The analysis of 8.3 avoided the same essential features of the divider which 7.7 omitted for the multiplier, and which were enumerated in 7.8:

(a)The timing network which controls the inputs t, t’, t’’, t’’'.

(b)The k (delay lengths) of the \(\boxed{dl Ⅰ}\) – \(\boxed{dl Ⅳ}\) The details differ from those in 7.8, (b), but the problem is closely parallel.

(c)The networks required to get the dividend and the divisor into \(\boxed{dl Ⅲ}\) and \(\boxed{dl Ⅰ}\) , and to get the quotient out of . \(\boxed{dl Ⅳ}\)

(d)The networks required to handle signs and binary point positions. As in the case of multiplication all these points will be dealt with subsequently.